1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to compilers for semiconductor memories with divided word lines and local wordline decoding circuitry disposed centrally in a memory instance.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a "design gap" between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the "deep submicron" problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other "non-logic" cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design re-use is through what are known as Intellectual Property ("IP") components--pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that the existing memory compilers are adequate for designing low density memory arrays e.g., 32 kbit, 64 kbit memories, etc. However, as arrays get larger for higher density by increasing in the X-direction (by adding additional columns or bitlines), Y-direction (by adding additional rows or wordlines), or both, parameters such as RC time delay, etc., which have a deleterious effect on the performance of a memory circuit, become significant in both directions of an array. Accordingly, it is common practice in the memory design art to segment the array in the Y-direction in order to provide additional sense amplifiers and associated column circuitry at predetermined locations across the memory array. That is, for every predetermined number of rows of wordlines, a horizontal band or strip of sense amplifier/column circuitry is provided along the Y-direction of the array. Consequently, the RC delay effects in the Y-direction are mitigated because the total length of bitline per sense amplifier is considerably reduced. This practice of segmenting the array vertically is sometimes referred to as "banking."
It is also known in the art to segment the wordlines in order to reduce the RC delay effects along the X-direction of the array. Typically, a local wordline decoder is provided at specific locations in the memory array along the X-direction which receives main wordline signals from a main row decoder. The main wordline signals are then decoded by the local wordline decoder in order to select a particular local row or wordline (or, sub-word line). This scheme is known in the industry as the "divided wordline" or DWL architecture.
Although advances such as those described above attempt to address the RC delay effects in large memory arrays, banking and DWL techniques have not been implemented together in the context of memory compilers which provide re-usable, tilable memory circuitry (preferably on a per I/O basis) for designing an array of an arbitrary size with a variable number of I/Os. Furthermore, it should be appreciated by those skilled in the art that the existing DWL techniques are beset with several deficiencies and shortcomings. First, current DWL architectures are unwieldy for memory circuits that employ dummy wordlines and/or dummy bitlines for ensuring certain signal levels on the active bitlines before the sense amplifiers read the data. It should be apparent that as the array expands in the X-direction, electrical characteristics of segmented wordlines in the main array, i.e., wordlines divided into main wordlines and local wordlines, cannot be accurately matched by the dummy wordlines without incurring area penalty due to additional control logic.
Moreover, as the array expands in the X-direction, tracking control logic signals on electrical paths that span the width of the array and are typically routed over highly variable circuit layout/geometry becomes very difficult. Accordingly, it would be highly advantageous to segment the control/peripheral circuitry into smaller units that provide tightly controlled signals for shorter spans of the array. However, such an arrangement requires additional area which the present memory architectures cannot accommodate.